An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

Author

Khamankar, R. ; Bu, H. ; Bowen, C. ; Chakravarthi, S. ; Chidambaram, P.R. ; Bevan, M. ; Krishnan, A. ; Niimi, H. ; Smith, B. ; Blatchford, J. ; Hornung, B. ; Lu, J.P. ; Nicollian, P. ; Kirkpatrick, B. ; Miles, D. ; Hewson, M. ; Farber, D. ; Hall, L. ; Als

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2004

Firstpage

162

Lastpage

163

Abstract

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12Å EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

Keywords

CMOS integrated circuits; MOSFET; carrier mobility; nanotechnology; 0.61 ps; 1.12 ps; 35 nm; 90 nm; enhanced 90nm high performance technology; implant profile; mobility; stress; strong performance improvements; transistors; Annealing; Dielectrics; Etching; Implants; MOS devices; MOSFETs; Material properties; Plasma applications; Space technology; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345456

Filename

1345456