Title :
International Test Conference 1989. Proceedings. Meeting the Tests of Time (Cat. No.89CH2742-5)
Abstract :
The following topics are dealt with: sequential ATPG (automatic test pattern generation); boundary scan algorithms; mixed signal testing; delay test generation; design and test in the university; pattern generation for built-in self-test; design for test of VLSI memories; signature analysis; hierarchical test generation; logic ATE (automatic test equipment) architecture; physical defects in VLSI chips; advances in fault simulation; and the economics of design for testability
Keywords :
VLSI; automatic test equipment; automatic testing; digital simulation; economics; electronic engineering computing; fault location; integrated circuit testing; integrated logic circuits; integrated memory circuits; logic CAD; logic testing; printed circuit testing; PCB testing; VLSI chips; VLSI memories; automatic test equipment; automatic test pattern generation; automatic testing; boundary scan algorithms; built-in self-test; delay test generation; design for testability; economics; electronic equipment testing; fault simulation; hierarchical test generation; logic ATE; logic testing; mixed signal testing; sequential circuits; signature analysis;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC, USA
DOI :
10.1109/TEST.1989.82255
