Title :
High performance CMOSFET technology for 45nm generation
Author :
Oishi, A. ; Komoda, T. ; Morimasa, Y. ; Sanuki, T. ; Yamasaki, H. ; Hamaguchi, M. ; Oouchi, K. ; Matsuo, K. ; Iinuma, T. ; Itoh, Takayuki ; Takegawa, Y. ; Iwai, M. ; Sunouchi, K. ; Noguchi, T.
Author_Institution :
Syst. LSI Div., Toshiba Corp., Yokohama, Japan
Abstract :
High performance CMOSFET process design for 45nm generation is demonstrated. Activation process policy is shown for the first time to achieve high performance source and drain extension (SDE) junction, high gate activation and defect-less source and drain (SD) junction simultaneously for 45nm generation technology. Most serious problem of phosphorus TED is investigated In detail and suppressed by appropriate designing of activation process. Good Vth roll-off and Ion-Ioff characteristics are achieved for 20nm gate MOSFET by utilizing ultra high speed annealing technique, disposable sidewall spacer, phosphorus n+ SD and appropriate designing of activation process.
Keywords :
CMOS integrated circuits; MOSFET; nanotechnology; 45 nm; 45nm generation; activation process policy; disposable sidewall spacer; high performance CMOSFET technology; high speed annealing technique; roll-off; source and drain extension junction; Annealing; CMOS technology; CMOSFETs; Crystallization; Electrodes; Fabrication; MOSFET circuits; Process design; Temperature; Thermal resistance;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345458
