Investigation of the junctionless line tunnel field-effect transistor

Author

Lei Yao ; Renrong Liang ; Chunsheng Jiang ; Jing Wang ; Jun Xu

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2014

fDate

7-10 May 2014

Firstpage

1

Lastpage

2

Abstract

The junctionless line tunnel field-effect transistor (JLL-TFET) is proposed, which makes use of carrier tunneling through a bias-induced electron-hole bilayer in the vertical direction. The JLL-TFET has a control gate and an auxiliary gate located in opposite directions with different work functions, which causes it to act as a vertical line tunneling field-effect transistor. In addition, this JLL-TFET is a junctionless transistor that has no conventional PN junction along the source-to-drain direction. The operating principle and electrical performance of the proposed JLL-TFET were investigated by 2-D numerical simulation.

Keywords

field effect transistors; tunnel transistors; work function; 2D numerical simulation; JLL-TFET; auxiliary gate; bias-induced electron-hole bilayer; carrier tunneling; control gate; electrical performance; junctionless line tunnel field-effect transistor; source-to-drain direction; vertical direction; vertical line tunneling field-effect transistor; work functions; Dielectrics; Electric fields; Junctions; Logic gates; Semiconductor process modeling; Transistors; Tunneling; junctionless field-effect transistor; line tunneling; tunnel field-effect transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Next-Generation Electronics (ISNE), 2014 International Symposium on

Conference_Location

Kwei-Shan

Type

conf

DOI

10.1109/ISNE.2014.6839326

Filename

6839326