• DocumentCode
    1611265
  • Title

    Soft error free, low power and low cost superSRAM with 0.98 μm2 cell by utilizing existing 0.15 μm-DRAM process

  • Author

    Fujii, Y. ; Ishigaki, Y. ; Hosokawa, T. ; Dei, M. ; Maki, Y. ; Nishida, A. ; Izutsu, T. ; Nakashima, Y. ; Toyota, R. ; Koga, T. ; Ipposhi, T. ; Konishi, Y. ; Kihara, Y.

  • Author_Institution
    LSI Manuf. Technol. Unit, Renesas Technol. Corp., Hyogo, Japan
  • fYear
    2004
  • Firstpage
    232
  • Lastpage
    233
  • Abstract
    16M-superSRAM with 0.98 μm2 is developed by existing 0.15 μm DRAM processes. As a result, the standby current and random access time of fabricated 16M-superSRAM are about 0.2 μA/chip and 43 ns at RT. As superSRAM has a cylindrical stacked capacitor at each node, very high tolerance for SER (soft error rate) is expected as compared with conventional 6Tr-SRAMs. By alpha ray irradiated experiments, an SER free feature of superSRAM is confirmed for the first time.
  • Keywords
    CMOS integrated circuits; DRAM chips; SRAM chips; 0.15 μm-DRAM process; 0.15 micron; 16 Mbit; 43 ns; cylindrical stacked capacitor; low cost superSRAM; random access time; standby current; Capacitors; Costs; Degradation; Driver circuits; Error analysis; Investments; Large scale integration; Random access memory; Substrates; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8289-7
  • Type

    conf

  • DOI
    10.1109/VLSIT.2004.1345497
  • Filename
    1345497
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1611265