A new vertically stacked poly-Si MOSFET with partially depleted SOI operation for densely integrated SoC applications

Vertical transistors take up less area than conventional planar CMOS devices and are thus promising as a means for increased densities of integration. Most of the vertical MOSFET structures proposed so far, however, require sophisticated processing which is incompatible with conventional CMOS processes. In this paper, we propose the use of a vertical poly-Si pMOSFET for SoC applications; this structure is easily stacked on bulk nMOS, eliminating the need for an n-well region and significantly reducing chip Size. The formation of poly-Si grain boundaries across the active channels of poly-Si MOSFETs means that these devices tend to exhibit poor performance in the form of large threshold-voltage fluctuations and large subthreshold swings. A vertical poly-Si transistor that operates with a partially depleted SOI structure and shows excellent DC characteristics has been developed as a solution to these problems. The impact of this new vertical pMOS structure on 6T-SRAM is also demonstrated.