Title :
Lane recognition system implemented by a full hardware design
Author :
Pin-Yang Kang ; Yen-Po Chen ; Ming-Jer Jeng
Author_Institution :
C Dept. of Electron. Eng., Chang Gung Univ., Taoyuan, Taiwan
Abstract :
In order to get a right decision instead of human eye, machine vision becomes a popular issue especially in the application field of automotive. This design provides a high speed lane recognition based on Terasic DE2-70 FPGA platform which included 4.3” touch LCD and a 500 Megapixel CCD camera. With full hardware design, this system can easily reduce the image processing and recognition time. The system with a relatively high rate of successful recognition under the 160 Km/hr can be achieved.
Keywords :
CCD image sensors; cameras; computer vision; field programmable gate arrays; object recognition; traffic engineering computing; CCD camera; Terasic DE2-70 FPGA platform; automotive application field; full hardware design; high speed lane recognition system; human eye; image processing; machine vision; touch LCD; Cameras; Educational institutions; Field programmable gate arrays; Flowcharts; Hardware; Image edge detection; FPGA; Hardware design; Lane recognition system;
Conference_Titel :
Next-Generation Electronics (ISNE), 2014 International Symposium on
Conference_Location :
Kwei-Shan
DOI :
10.1109/ISNE.2014.6839353
