Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

Author

Specht, M. ; Kömmling, R. ; Dreeskornfeld, L. ; Weber, W. ; Hofmann, F. ; Alvarez, D. ; Kretz, J. ; Luyken, R.J. ; Rösner, W. ; Reisinger, H. ; Landgraf, E. ; Schulz, T. ; Hartwich, J. ; Städele, M. ; Klandievski, V. ; Hartmann, E. ; Risch, L.

Author_Institution

Infineon Technol. AG, Munich, Germany

fYear

2004

Firstpage

244

Lastpage

245

Abstract

Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L_G = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.

Keywords

flash memories; semiconductor storage; 30 to 80 nm; NAND-type array organization; On-state; high resolution scanning spreading resistance microscopy; high-density applications; sub-40nm tri-gate charge trapping nonvolatile memory cells; tri-gate memory device; Dry etching; Electric resistance; Electric variables; Electrostatics; Flash memory; Lithography; Microscopy; Nonvolatile memory; Threshold voltage; Visualization;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345504

Filename

1345504