Simultaneous data path synthesis and clock skew scheduling for leakage and glitch power minimization

In this paper, we point out that, in addition to data path synthesis (gate sizing and buffer insertion), clock skew can also be utilized for further power reduction. We propose an integer linear programming for the simultaneous application of data path synthesis and clock skew scheduling. Note that our approach is the first work to deal with this problem. Compared with previous works, our approach can achieve better results.