Logical fault modeling of source drain short defects for CMOS reversible circuits

Author

Boncalo, Oana ; Amaricai, Alexandru

Author_Institution

Comput. Eng. Dept., Univ. Politeh. of Timisoara, Timisoara, Romania

fYear

2010

Firstpage

482

Lastpage

485

Abstract

We propose logic level fault models of the source*drain resistive short defect for reversible circuits. The devices are implemented with CMOS transmission gates in a dual logic manner. The models are determined based on static SPICE simulations of three reversible gates: Controlled-Not, Toffoli and Fredkin. Test vectors for detecting these faults are also given. The goal is to devise Boolean test strategies for reversible circuits as well as logic level assessment of fault tolerance.

Keywords

CMOS integrated circuits; fault simulation; integrated circuit modelling; logic gates; Boolean test strategies; CMOS reversible circuits; CMOS transmission gates; Fredkin gates; Toffoli gates; controlled-not gates; dual logic manner; fault tolerance; logic level assessment; logical fault modeling; source drain short defects; static SPICE simulation; CMOS integrated circuits; Circuit faults; Computational modeling; Integrated circuit modeling; Logic gates; Semiconductor device modeling; Testing; Fault models; Reversible gates; Short Defects; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference

Conference_Location

Warsaw

Print_ISBN

978-1-4244-7011-2

Electronic_ISBN

978-83-928756-4-2

Type

conf

Filename

5551301