A universal model for calculating capacitive and resistive coupling on lightly and heavily doped CMOS processes

Author

Bontzios, Yiorgos I. ; Hatzopoulos, Alkis

Author_Institution

Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2010

Firstpage

49

Lastpage

53

Abstract

A new model for calculating capacitive and resistive coupling is developed in this work and its implementation in commonly encountered practical cases is presented. The model is based on the geometry of the coupling mechanism and is therefore, in general, scalable and technology independent, while pure 3D effects, like capacitive coupling, are fast and accurately computed. The proposed model is validated using measurements from a test chip in the UMC 0.18-μm CMOS lightly doped process, simulation data obtained by two commercial simulators and theoretical results. The accuracy of the model is shown to be within 2-10%.

Keywords

CMOS integrated circuits; coupled circuits; integrated circuit modelling; UMC CMOS processes; capacitive coupling calculation; commercial simulators; heavily doped CMOS process; lightly doped CMOS process; resistive coupling calculation; simulation data; size 0.18 mum; test chip; Capacitance; Computational modeling; Couplings; Mathematical model; Resistance; Semiconductor device modeling; Substrates; CMOS integrated circuits; Geometric modeling; Integrated circuit noise; Substrate coupling;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference

Conference_Location

Warsaw

Print_ISBN

978-1-4244-7011-2

Electronic_ISBN

978-83-928756-4-2

Type

conf

Filename

5551302