The efficient circuit delay evaluation/diagnosis methodology under voltage drop

Voltage-drop is a well-known signal integrity issue in very deep submicron technology. Voltage drop does not only induce circuit delay, but also reduces the circuit noise margins from lower supply voltages and creates reliability issues from electromigration. Voltage drop occurs due to the insufficient current supplied under design circuit state transitions. In this paper, a maximum transition current computation tool is developed. The proposed PIPD is a gate level path delay analysis tool used under insufficient current supplied conditions. This tool could help designers to quickly compute/estimate the longest path delay when voltage drop issues occur. With regard to this research issue, past works are pattern independent, which are worst-case assumptions. PIPD use a real functional test bench to activate gate transitions´ peak current. The circuit peak current being accurate estimated in this research, which confirmed that dynamic behavior is pattern dependent. The proposed pattern dependent method is more realistic, and the measurement results might be lower and more accurate than earlier works. Using a PIPD could help design reasonable power rails. The simulation results prove that PIPD gate-level computation results are very close to the HSPICE transistor-level simulation results, with the average differing ratios being less than 8%, while the computation speed is increased 10X. Different to conventional EDA tools, PIPD also found that voltage drop is not certain to impact circuit delay times and calibrated by several real designed circuits.