Applications of plan-view TEM analysis to IC debugging

Author

Hsieh, Y.F. ; Chen, J.C. ; Lo, C.K. ; Wu, Y.R. ; Chiu, J.F.

Author_Institution

Mater. Anal. Technol. Inc., Hsin-Chu, Taiwan

fYear

2004

Firstpage

33

Lastpage

36

Abstract

In this report, applications of plan-view TEM analyses to IC debugging has been applied to some FA cases, where frequently used tools, such as SEM, FIB, AFM, etc., are not able to reveal the crystalline defects buried in the Si substrate. The novel examples include IC process induced oxidation stacking faults, sidewall profile of shallow trench isolation (STI), aggressive layout design induced active-to-active area breakdown, mask design error induced improper ion implantation, ESD failure induced local bum-out, and metal silicide encroachment.

Keywords

electrostatic discharge; failure analysis; integrated circuit testing; ion implantation; isolation technology; oxidation; semiconductor device breakdown; transmission electron microscopy; ESD failure; IC manufacturing; IC process debugging; STI sidewall profile; active-to-active area breakdown; improper ion implantation; local burn-out; mask design error; metal silicide encroachment; plan-view TEM analysis; process induced oxidation stacking faults; shallow trench isolation; substrate buried crystalline defects; Application specific integrated circuits; Crystallization; Debugging; Electric breakdown; Electrostatic discharge; Integrated circuit layout; Ion implantation; Oxidation; Silicides; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the

Print_ISBN

0-7803-8454-7

Type

conf

DOI

10.1109/IPFA.2004.1345530

Filename

1345530