Title :
Circuit partitioned automatic test pattern generation constrained by three-state buses and restrictors
Author :
Van der Linden, J. Th ; Konijnenburg, M.H. ; van de Goor, A.J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external restrictions and exclusions on test patterns. A cone-oriented circuit partitioning method dealing with these problems is proposed. A serial ATPG scheme for the partitions is proposed. The combined effectiveness is shown by experimental results
Keywords :
automatic testing; integrated circuit testing; logic partitioning; logic testing; multivalued logic circuits; ATPG; bus-conflict-free tests; circuit partitioned automatic test pattern generation; circuit sizes; cone-oriented partitioning; restrictors; three-state buses; Automatic test pattern generation; Circuit faults; Circuit testing; Clustering algorithms; Driver circuits; Hardware; Logic circuits; Logic gates; Partitioning algorithms; Test pattern generators;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555132
