DISC: dynamic instruction stream computer-an evaluation of performance

DISC is a simple processor architecture targeted for real-time applications. The architecture is based on dynamic fine-grained multithreading where the next instruction is fetched from one of several possible simultaneously active threads. The DISC architecture uses a combination of concepts including, a register stack file, a four stage pipeline, up to four active threads, a dynamic scheduler, and special input/output (I/O) and interrupt constructs to allow maximization of performance for real-time control applications. Previous stochastic results were very encouraging and so a synthetic benchmark was developed to allow more detailed testing. The benchmark was based on a Hughes Aircraft Company satellite control system, and assembled with the DISC assembler. The model was designed and run in the Verilog simulation language.