The design of a high-performance cache controller: a case study in asynchronous synthesis

The authors integrated two distinct approaches in asynchronous system design: the design of controllers and the design of processor architectures. In earlier work, S.M. Nowick and D.L. Dill (1991) presented a new method for the synthesis of locally clocked asynchronous controllers, and the STRiP architecture was shown by M.E. Dean (1992) to provide an attractive alternative to comparable synchronous and asynchronous implementations. However, to support this asynchronous paradigm, an efficient asynchronous memory subsystem is critical. Here, the locally clocked synthesis method is applied to the design of an asynchronous second-level cache controller. The authors demonstrate the feasibility of the proposed locally clocked method for the design of a substantial real-world controller, show how such a controller can support the asynchronous external interface of an asynchronous RISC architecture, and present a cache controller which is significantly faster than a comparable synchronous design. Cache-access latency in the design is 50% less than for an equivalent synchronous implementation.