Specification, simulation, and synthesis of self-timed circuits

The authors present an integrated design environment called SHILPA for the specification, simulation, analysis, and synthesis of self-timed asynchronous circuits. In SHILPA, behavioral specifications can be written in a hardware description language (HDL) called hopCP, subject to efficient compiled-code functional simulation, compiled into a flow graph representation, and subject to flow-analysis to detect serial actions. Thereafter, the flow-graph can be compiled into a netlist for the Actel field programmable gate array (FPGA) through a series of refinement steps. The authors illustrate SHILPA on a multiplier circuit and also pipelining through program transformation on the multiplier as well as min-max circuit.