Design of a delay-insensitive multiply-accumulate unit

The design and implementation of a serial-parallel multiply-accumulate unit using a method and tools developed for design of delay-insensitive circuits are described. In the class of asynchronous circuits the functional correctness is independent of any delays in circuit elements and wires, except for certain known isochronic wire forks. An objective in asynchronous design is to attain the best possible average performance and to use this potential performance advantage already at the architectural level. The authors have designed the multiply-accumulate unit to exploit this objective. The full course of design from a high-level description to fabrication is illustrated. This includes the optimization considerations at each level of abstraction from the top to the bottom.