Title :
Low k damage control & its reliability for organic hybrid dual damascene
Author :
Su, Y.N. ; Shieh, J.H. ; Hsu, P.F. ; Lin, K.C. ; Chiou, W.C. ; Kuo, H.H. ; Tao, H.J. ; Liang, M.S.
Author_Institution :
Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
A hybrid dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. The traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ultra-low-k. Our approach is able to circumvent the issues mentioned above without introducing process complication. Good sheet resistance control is obtained for trench etch without a middle stop layer. And good via resistance yield with good thermal stability is obtained as well. 21% of RC product reduction is obtained when it is compared with the PR approach for CVD ultra-low-k.
Keywords :
chemical vapour deposition; copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; thermal stability; CVD; Cu; RC product reduction; ashing damage; copper-low-k interconnects; damascene interconnect; dielectric reliability; low-k damage control; organic hybrid dual damascene; organic ultra-low-k gap filling; sheet resistance control; thermal stability; trench etch; via resistance yield; via-first process; Ash; Dielectric materials; Etching; Filling; Leakage current; Manufacturing industries; Planarization; Research and development; Semiconductor device manufacture; Thermal stability;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345544
