Title :
Stress-induced voiding beneath vias with wide copper metal leads
Author :
Lim, Y.K. ; Lim, Y.H. ; Kamat, N.R. ; See, A. ; Lee, T.J. ; Pey, K.L.
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore
Abstract :
The phenomenon of stress-induced voiding beneath vias with wide copper (Cu) metal leads was studied using via chain structures stressed at temperatures ranging from 150°C to 200°C. After a 1000-hour stress migration (SM) test, via chain structures with extremely high resistance were mainly observed at the edge of the wafer. In addition, it was found that the geometrical dependency of stress-induced voiding could possibly be eliminated with increased process robustness. Dual-via interconnects were also proven to improve SM performance and for the first time, advanced physical analysis techniques were employed to study the cause of the improvement.
Keywords :
copper; electric resistance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; internal stresses; voids (solid); 1000 hour; 150 to 200 degC; Cu; dual-via interconnects; high resistance via chain structures; stress migration; stress-induced voiding; voiding geometrical dependency; wide copper metal leads; Annealing; Artificial intelligence; Atherosclerosis; Copper; Dielectrics; Lead; Robustness; Samarium; Stress; Very large scale integration;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345556
