Thermal laser stimulation effects on NMOS transistor

Thermal laser stimulation techniques allow localizing defects on integrated circuits from front side and backside. Sometimes, the understanding of signatures given by these mapping techniques appears difficult. Their interpretations are often referenced from simple structures such as metal lines. Understanding of TLS signatures on elementary MOS transistors, seems to be necessary. This study is based on thermal laser effects on a NMOS transistor operated in the saturation regime. The drain current variation upon laser heating is reported. Experimental results obtained on the PHEMOS 1000 system from Hamamatsu are presented.