Title :
Parallel architectures for high speed multipliers
Author :
Maden, B. ; Guy, C.G.
Author_Institution :
Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK
Abstract :
The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes
Keywords :
counting circuits; emitter-coupled logic; multiplying circuits; parallel architectures; array multiplier architectures; carry-save array; complexity; conventional full-adder; counter cell; counter circuits; high speed multipliers; increasing speed; modern emitter-coupled-logic processes; multiplier design; Adders; Complexity theory; Counting circuits; Educational institutions; Encoding; Energy consumption; Integrated circuit interconnections; Parallel architectures; Silicon; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100312
