A 26.5 GHz PLL synthesizer with low phase noise characteristics

Author

Chenakin, Alexander ; Ojha, Suresh ; Nediyanchath, Shyam

Author_Institution

Phase Matrix, Inc., San Jose, CA, USA

fYear

2011

Firstpage

1210

Lastpage

1213

Abstract

A novel PLL frequency synthesizer architecture is presented. The proposed architecture offers improved phase noise characteristics by removing frequency division from the PLL feedback path. This minimizes the impact of the phase detector residual noise floor. Moreover, phase noise can be further improved by inserting a frequency multiplier into the feedback path. A 5 MHz to 26.5 GHz synthesizer module based on the proposed architecture has been developed. Phase noise at 26.5 GHz output and 10 kHz offset is measured at -110 dBc/Hz. The measured spurs do not exceed -60 dB level. The switching time is less than 100 microseconds for any frequency step within the entire operating range.

Keywords

frequency dividers; frequency multipliers; frequency synthesizers; phase locked loops; phase noise; PLL feedback path; PLL frequency synthesizer architecture; PLL synthesizer; frequency 5 GHz to 26.5 GHz; frequency division; frequency multiplier; frequency step; low phase noise characteristics; phase detector residual noise floor; switching time; synthesizer module; Detectors; Frequency synthesizers; Mixers; Phase locked loops; Phase noise; Synthesizers; Frequency divider; frequency synthesizer; noise floor; phase detector; phase noise; voltage-controlled oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2011 Asia-Pacific

Conference_Location

Melbourne, VIC

Print_ISBN

978-1-4577-2034-5

Type

conf

Filename

6173975