Title :
A systolic power-of-two multiplier structure
Author :
Tseng, Ching Yih ; Griffiths, L.J.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ of Southern California, Los Angeles, CA, USA
Abstract :
A power-of-two multiplier with a fully pipelined structure is presented. The design is based on dividing the multiplication into three succeeding stages so that no bit accumulation occurs in any of them. The only nontrivial part of this multiplier is the implementation of the second stage, which requires a fully pipelined shifter. A design example of the shifter is presented to demonstrate the mechanism of the shifter when the input data path is 2 b. Generalizing this technique to a multiplier with an input data path of an arbitrary number of bits simply involves properly extending the size of the circuit and changing the controlled parameters and clocking schemes
Keywords :
cellular arrays; multiplying circuits; pipeline processing; bit accumulation; clocking schemes; controlled parameters; fully pipelined shifter implementation; input data path; multiplication stages; multiplier circuit size; pipelined structure; shifter design; shifter mechanism demonstration; systolic power-of-two multiplier structure; technique generalization; Arithmetic; Circuits; Costs; Digital signal processing; Hardware; Quantization; Semiconductor device noise; Signal processing algorithms; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100313
