DocumentCode
1613016
Title
Backside failure analysis and case studies for Cu/low k technology
Author
Wu, Huixian ; Cargo, James
Author_Institution
Product Anal. Lab., IC Quality Organ., Allentown, PA, USA
fYear
2004
Firstpage
127
Lastpage
134
Abstract
In this work, failure analysis (FA) challenges and new failure modes for devices of copper technology, especially for circuit-under-pad (CUP) devices are presented. Backside FA techniques including backside sample preparation, backside defect localization, backside physical analysis with both deprocessing and cross section analysis have been developed and applied to Cu/low k technology. For backside FA deprocessing, we present wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the backside FA cross-section analysis of copper/low k samples, focused ion beam (FIB) techniques that have been developed and studied are addressed. In addition, detailed characterization of backside silicon thinning using TMAH wet chemicals is presented.
Keywords
chemical mechanical polishing; copper; dielectric thin films; etching; failure analysis; fault location; focused ion beam technology; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; permittivity; plasma materials processing; specimen preparation; sputter etching; CMP; CUP devices; Cu; Cu/low k technology; FIB; RIE; TMAH wet chemicals; backside FA cross-section analysis; backside FA deprocessing; backside defect localization; backside failure analysis; backside physical analysis; backside silicon thinning; chemical mechanical polishing; circuit-under-pad devices; copper technology; deprocessing; failure modes; focused ion beam techniques; parallel polishing; reactive ion etching; wet chemical etching; Chemical technology; Chip scale packaging; Computer aided software engineering; Copper; Dielectric materials; Electric resistance; Failure analysis; Integrated circuit interconnections; Integrated circuit technology; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN
0-7803-8454-7
Type
conf
DOI
10.1109/IPFA.2004.1345568
Filename
1345568
Link To Document