High performance instruction memory design for multiprocessors

Current large-scale multiple instruction, multiple data (MIMD) machines use the single program, multiple data (SPMD) execution mode, in which processors have the same code image but may follow distinct flow paths. The authors propose a simple scheme that exploits this fact and improves earlier work by providing additional, computer-driven control of the instruction memory system to support a scalable multiprocessor architecture with a single, global instruction memory. Compiler-generated tags, combined with straightforward, compiler flow analysis, allow additional control of the cache to prevent cache pollutions and to allow small caches to attain the same performance as much larger caches.