Title :
SOI devices for sub-0.1 μm gate lengths
Author :
Colinge, J.P. ; Park, J.T. ; Colinge, C.A.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
Different SOI MOSFET structures for sub 0.1 μm gate lengths are discussed. To reduce short-channel effects such as DIBL (drain induced barrier lowering) and subthreshold slope degradation, thin SOI films have to be used, which causes high source and drain resistance and low threshold voltage problems. These problems can be solved using midgap gate materials, elevated or Schottky S and D structures and multiple gates. The use of ground-plane structures improves the short-channel effects but increase the body effect, while the use of multiple gates (double gate, triple gate, etc.) improves all device characteristics and increase the current drive. SOI seems well adapted to future low-power VLSI electronics.
Keywords :
MOS integrated circuits; MOSFET; Schottky barriers; VLSI; electric resistance; low-power electronics; semiconductor thin films; silicon-on-insulator; 0.1 micron; DIBL; MOSFET gate lengths; SOI MOSFET current drive; SOI MOSFET structures; SOI device characteristics; Schottky S/D structures; Si-SiO2; body effects; double gate structures; drain induced barrier lowering; drain resistance; elevated source/drain structures; ground-plane structures; low-power VLSI electronics; midgap gate materials; multiple gate structures; short-channel effects; source resistance; subthreshold slope degradation; thin SOI films; threshold voltage problems; triple gate structures; Etching; Fabrication; Implants; Length measurement; MOSFET circuits; Semiconductor films; Silicon; Substrates; Thickness measurement;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003156
