Multilevel Structured Low-Density Parity-Check Codes

Low-density parity-check (LDPC) codes are typically characterized by a relatively high-complexity description, since a considerable amount of memory is required in order to store their code description, which can be represented either by the connections of the edges in their Tanner graph or by the non-zero entries in their parity-check matrix (PCM). This problem becomes more pronounced for pseudo-random LDPC codes, where literally each non-zero entry of their PCM has to be enumerated, and stored in a look-up table. Therefore, they become inadequate for employment in memory- constrained transceivers. Motivated by this, we are proposing a novel family of structured LDPC codes, termed as Multilevel Structured (MLS) LDPC codes, which benefit from reduced storage requirements, hardware-friendly implementations as well as from low-complexity encoding and decoding. Our simulation results demonstrate that these advantages accrue without any compromise in their attainable Bit Error Ratio (BER) performance, when compared to their previously proposed more complex counterparts of the same code-length. In particular, we characterize a half-rate quasi-cyclic (QC) MLS LDPC code having a block length of 8064 that can be uniquely and unambiguously described by as few as 144 edges, despite exhibiting an identical BER performance over both Additive White Gaussian Noise (AWGN) and uncorrelated Rayleigh (UR) channels, when compared to a pseudorandom construction, which requires the enumeration of a significantly higher number of 24,192 edges.