Title :
A 4-transistor static memory cell design with a standard CMOS process
Author :
Ni, Yang ; Devos, F.
Author_Institution :
Inst. d´´Electron. Fondamentale, Univ. de Paris Sud, Orsay, France
Abstract :
A static four-transistor memory cell design which can be implemented with a standard CMOS process is presented. By combining dynamic read/write memory operations and static data memorization, no refresh is needed for the memory matrix. With a small cell surface and compatibility with the CMOS logic implementing process, it is very adequate to apply this memory cell design to the onchip memory or register file in DSP VLSI design. A 128-b×8-b experimental memory chip is being fabricated in the French MPC CMOS process with a 2-μm design rule, and the memory cell occupies a surface of 690 μm2 , which is equivalent to that of a four-transistor dynamic cell
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; integrated memory circuits; random-access storage; 128-b×8-b experimental memory chip; 2 micron; CMOS logic implementing process compatibility; DSP VLSI design; French MPC CMOS process; design rule; dynamic read/write memory operations; memory cell design; memory cell size; memory matrix; onchip memory; register file; small cell surface; standard CMOS process; static data memorization; static four-transistor memory cell design; CMOS logic circuits; CMOS process; Digital signal processing chips; Logic design; Microprocessors; Random access memory; Read-write memory; Registers; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100317
