SPICE simulation of electro-thermal effects in new-generation multicellular VDMOS transistors

In this paper a novel SPICE-based simulation tool is presented, suitable to describe the steady-state electro-thermal behavior of new-generation multicellular VDMOS transistors for low-voltage applications. Compared to similar approaches, the proposed one presents substantial improvements: (a) a new electrothermal sub-circuit representation for the elementary transistor is used, which provides an accurate prediction of device characteristics over the temperature range [300 K-400 K] also in quasi-saturation operating mode; (b) the thermal network accounts for both self-heating and thermal interaction effects, is based solely on layout data and is automatically generated; (c) non linear thermal phenomena and layout effects are taken into account.