Implementation of DCT for video compression with reconfigurable technology

Author

Chung, Yuk Ying ; Bergmann, Neil W.

Author_Institution

Space Centre for Satellite Navigation, Queensland Univ. of Technol., Brisbane, Qld., Australia

Volume

2

fYear

1997

Firstpage

441

Abstract

Describes the implementation of discrete cosine transform (DCT) algorithms for video compression using reconfigurable logic technology. We present two approaches for the implementation of the DCT. We discuss their time and area limits using Xilinx 4010 look-up table (LUT) based field programmable gate array (FPGA). The result shows a 50% area reduction or 2 times throughput improvement if we use distributed arithmetic instead of conventional arithmetic to implement DCT using LUT-based FPGA

Keywords

data compression; digital arithmetic; digital signal processing chips; discrete cosine transforms; distributed algorithms; field programmable gate arrays; image processing equipment; reconfigurable architectures; table lookup; transform coding; video coding; video equipment; DCT; FPGA; Xilinx 4010 look-up-table based field programmable gate array; area limits; discrete cosine transform algorithms; distributed arithmetic; reconfigurable logic technology; throughput improvement; time limits; video compression; Arithmetic; Discrete cosine transforms; Field programmable gate arrays; Hardware; Image coding; Programmable logic arrays; Space technology; Table lookup; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications., Proceedings of IEEE

Conference_Location

Brisbane, Qld.

Print_ISBN

0-7803-4365-4

Type

conf

DOI

10.1109/TENCON.1997.648211

Filename

648211