Simulation, synthesis, and verification of pipelined asynchronous VLSI circuits

Systolic arrays are a powerful implementation method for signal, image and video processing algorithms which operate on continuous data streams. While systolic arrays assume a synchronous clocking scheme, similar regular pipelined processing networks can be based on an asynchronous timing model, with resulting advantages in terms of modularity, speed, and power consumption. Unfortunately there is little expertise or CAD support for the system level design of asynchronous pipelined data networks. This paper presents a modelling methodology for these networks based on functions operating on lists of data values, allowing computations to be described in terms of the sequence of data values processed without explicitly assigning times to the individual operations. It describes strategies and accompanying CAD tools for using this methodology for system specification, simulation, verification, and synthesis