Failure mechanism of smaller substrate bond pad size in flip chip technology

Author

Chen, CheeKoang ; Cheah, SeawLai ; Ang, ToonYoon ; Singh, Kuljeet ; Earley, Anita A.

Author_Institution

Intel Corporate, Penang, Malaysia

fYear

2004

Firstpage

235

Lastpage

238

Abstract

The solution to the increasing demands for miniaturisation could be accomplished through flip chip interconnection technology. It is known that substrate solder resist opening is one of the key designs that govern a product size to increase I/O density. With the reduction of its size, it posed chip joint necking reliability issues. Interaction of substrate solder volume (package), package and die bump void (silicon/chip) was identified as the cause of this issue. The solution for this issue is critical in supporting future product trends of demanding high I/O density design.

Keywords

failure analysis; flip-chip devices; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; microassembling; necking; soldering; voids (solid); chip joint necking reliability; die bump void; failure mechanism; flip chip interconnection technology; flip chip technology; high I/O density design; miniaturisation; product size; substrate bond pad size; substrate solder resist opening; substrate solder volume; Atherosclerosis; Bonding; Costs; Failure analysis; Flip chip; Lead; Resists; Semiconductor device packaging; Substrates; Surface-mount technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the

Print_ISBN

0-7803-8454-7

Type

conf

DOI

10.1109/IPFA.2004.1345607

Filename

1345607