Reliability and device scaling challenges of trapping charge flash memories

Author

Yeh, C.C. ; Tsai, W.J. ; Lu, Chih-Yuan ; Liao, Y.Y. ; Zous, N.K. ; Chen, H.Y. ; Wang, Tahui ; Ting, WenChi ; Ku, Joseph ; Chih-Yuan Lu

Author_Institution

Technol. Dev. Center, Macronix Int. Co. Ltd., Hsin-Chu, Taiwan

fYear

2004

Firstpage

247

Lastpage

250

Abstract

As flash memories move toward the giga-bits era, several challenges limit their scalability. Floating gate flash memories face the problems of un-scalable tunnel oxide, and the last technology node of NOR flash was predicted to be 65 nm, based on the extrapolation of the difference between physical and electrical cell dimensions vs. generations, which drops to zero at 45 nm. Although SONOS-type flash memories show better scalability and simpler process, there are still some difficulties. In this paper, three SONOS-type flash memories (SONOS, NROM and PHINES) are compared and the scaling problems and reliability issues are disclosed.

Keywords

dielectric thin films; flash memories; integrated circuit design; integrated circuit reliability; integrated memory circuits; read-only storage; 45 nm; 65 nm; NOR flash; NROM; PHINES; SONOS-type flash memories; SiO₂-Si₃N₄-SiO₂; device scaling; electrical cell dimensions; extrapolation; floating gate flash memories; physical cell dimensions; reliability; scalability; technology node; trapping charge flash memories; unscalable tunnel oxide; Channel hot electron injection; Electron traps; Electronics industry; Extrapolation; Flash memory; Industrial electronics; Nonvolatile memory; Reliability engineering; SONOS devices; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the

Print_ISBN

0-7803-8454-7

Type

conf

DOI

10.1109/IPFA.2004.1345612

Filename

1345612