Title :
A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation
Author :
Tanaka, Nagataka ; Naruse, Junji ; Mori, Akiko ; Okamoto, Ryuta ; Yamashita, Hirofumi ; Monoi, Makoto
Author_Institution :
Toshiba Semicond., Yokohama
Abstract :
In this paper, a shared-pixel architecture in which the Gr pixel and the Gb pixel are designed to have the same layout structure, is introduced for suppression of the Gr/Gb sensitivity imbalance. In addition, a more effective FD-boost scheme that uses both gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) is introduced to resolve the trade-off between dark random noise and FD capability, without adding any additional pixel-drive wiring.
Keywords :
CMOS image sensors; -to-drain capacitance; CMOS image sensor; gate-to-source capacitance; layout structure; shared-pixel architecture; CMOS image sensors; Computational fluid dynamics; Electrons; Image sensors; Photodiodes; Pixel; Semiconductor device noise; Turning; Voltage; Wires;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977299
