An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications

Key elements for machine vision are the intra-scene dynamic range of the optical front-end, and a data representation that is as independent as possible from the illumination level. Furthermore, combining an optical front-end and a processor on the same chip enables a single-chip vision system to perform image acquisition, analysis and decision-making. This paper presents a system-on-chip which combines a front-end pixel with a time-domain logarithmic encoding and a variable reference voltage, a 32b processor, a graphical processing unit, 128 KB or SRAM, and several communication interfaces.It offers a 132dB intra-scene dynamic range encoded logarithmically with 149 steps per decade while achieving an FPN of 0.51 LSB. Logarithmic encoding is exploited on-chip to efficiently compute the image contrast by simple subtractions between neighbouring pixels.