Title :
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms
Author :
Duganapalli, Kishore ; Palit, Ajoy K. ; Anheier, Walter
Author_Institution :
ITEM, Univ. of Bremen, Bremen, Germany
Abstract :
The coupling noise between adjacent interconnects has become major SI issue, due to higher aspect ratios of interconnects in DSM chips, giving rise to crosstalk failures. The Genetic Algorithms (GA) have been applied earlier in different engineering disciplines as potentially good optimization tools and also for various applications in VLSI Design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.
Keywords :
automatic test pattern generation; fault diagnosis; genetic algorithms; integrated circuit interconnections; integrated circuit noise; integrated circuit testing; logic testing; ATPG tool; DSM chip; EDIF digital system testing; GA; VLSI design; automatic test pattern generation; chips interconnect; coupling noise; crosstalk-induced delay fault; elitist GA; genetic algorithm; on-chip aggressor; on-chip victim; stuck-at-fault; test automation; very large scale integration; Biological cells; Circuit faults; Crosstalk; Genetic algorithms; Logic gates; Sociology; Statistics; ATPG; Crosstalk; Genetic Algorithms;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-6779-7
DOI :
10.1109/DDECS.2015.34
