• DocumentCode
    1614410
  • Title

    A 45nm 8-core enterprise Xeon® processor

  • Author

    Rusu, Stefan ; Tam, Simon ; Muljono, Harry ; Stinson, Jason ; Ayers, David ; Chang, Jonathan ; Varada, Raj ; Ratta, Matt ; Kottapalli, Sailesh

  • Author_Institution
    Intel, Santa Clara, CA
  • fYear
    2009
  • Firstpage
    56
  • Lastpage
    57
  • Abstract
    The next-generation enterprise Xeonreg server processor consists of eight dual- threaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. This design has 2.3B transistors and is implemented in 45 nm CMOS using metal-gate high-K dielectric transistors and nine Cu interconnect layers. The thermal design power is 130 W.
  • Keywords
    CMOS integrated circuits; microprocessor chips; Nehalem cores; interconnect layers; metal-gate high-K dielectric transistor; multiple system topologies; next-generation enterprise Xeon server processor; on-chip memory controller; power 130 W; size 45 nm; system interface; thermal design; CMOS technology; Clocks; Counting circuits; Microprocessors; Packaging; Resistors; Subthreshold current; Testing; Tracking loops; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-3458-9
  • Type

    conf

  • DOI
    10.1109/ISSCC.2009.4977305
  • Filename
    4977305
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1614410