• DocumentCode
    1614433
  • Title

    32nm yield learning using efficient parallel-test structures

  • Author

    Karthikeyan, Muthu ; Medina, Louis ; Shiling, Ernesto ; Kiesling, David

  • Author_Institution
    IBM Syst. & Technol. Group, Hopewell Junction, NY, USA
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The continuing rise in the number and complexity of test structures required to characterize every new technology generation demands at least a commensurate increase in test throughput. At IBM, various 32nm yield test structures are being tested on a functional test platform using customized Source Measurement Units (SMU) that allow parallel current measurement on up to 100 pins. This novel method improves test throughput as much as 9X over traditional parametric testing while offering current measurement resolution down to 100 fA. The test structures described herein help accelerate yield learning by enabling characterization of yield-loss mechanisms and rapid evaluation of yield improvement actions.
  • Keywords
    integrated circuit testing; integrated circuit yield; monolithic integrated circuits; parallel-test structures; size 32 nm; source measurement units; yield learning; yield-loss mechanisms; Current measurement; Electrical resistance measurement; Probes; Resistance; Semiconductor device measurement; Testing; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI
  • Conference_Location
    San Francisco, CA
  • ISSN
    1078-8743
  • Print_ISBN
    978-1-4244-6517-0
  • Type

    conf

  • DOI
    10.1109/ASMC.2010.5551411
  • Filename
    5551411