Dynamic frequency-switching clock system on a quad-core Itanium® processor

The700mm² 65nm Itanium^reg processor codenamed Tukwila integrates four cores and a system interface with six QuickPath^reg interconnect channels and four memory interconnect channels. The large die and high level of integration coupled with process variability present clock-system design challenges in the areas of power consumption and variability compensation that discuss in this paper. The clock system, which is a cascaded-PLL architecture with an initial filter PLL that receives a 133 MHz reference clock. This maiden PLL filters reference-clock jitter and outputs a 133 MHz clock to 13 downstream PLLs. Each downstream PLL has a duty-cycle corrector that monitors and corrects the end-of-route duty cycle.