An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

This paper introduces a reconfigurable MIMO V-BLAST (vertical Bell Laboratories layered space-time) square root decoder that is CORDIC operators based, allows for dynamically changing the interconnections between the CORDIC (coordinate rotation digital computer) operators. These interconnections of CORDIC operators are implemented in a partial reconfigurable part of FPGA using the dynamic reconfiguration method which improves both the reconfiguration time and the area efficiency. Moreover, this reconfiguration time improvement is increased thanks to the MicroBlaze (within the FPGA) in which is included the reconfiguration management. This MIMO square root decoder is mapped on a Xilinx Virtex-4, showing the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.