PLDs implementation of islanding detection for grid connected inverter

This paper presents the programmable logic devices implementation of islanding detection for grid connected inverter with under/over voltage and under/over frequency islanding detection algorithms. The design are based on the field programmable gate array (FPGA) and the complex programmable logic device (CPLD). The logic circuits inside PLDs chip are design, implementation, testing and debugging by software development without hardware modification. The prototypes of PLDs for islanding detection are monitor the grid voltage and grid frequency at the point of common coupling (PCC) between the grid connected inverter, the local load and the distribution transformer and processed the value of voltage and frequency for turned on - off relay between grid connected inverter and utility grid. The results of study, the prototypes can turn off relay when the voltage is change under 200V or over 240V and frequency is change under 48Hz or over 52Hz. The FPGA-based is operated faster and high capacity than CPLD-based but the cost of design is higher.