A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.