Tradeoff decisions made for a P1149.1 controller design [ATE]

The author documents tradeoffs involved in designing an IEEE P1149.1/Joint Test Action Group (JTAG) scan bus master (SBM) that can operate at 25 MHz and interfaces a parallel host processor data bus to the serial P1149.1 test bus. By controlling the bits and all P1149.1 protocol for the host through an external device, the speed of running tests and scanning data is increased. Speed and throughput improve as more functions are implemented in controller hardware and fewer in host processor software. However, some advanced features require additional pins. Since the desired goals were a smaller part to fit more easily in a UUT (unit under test) and lower device cost, not all of the high-end functions were attained. The goals for the SBM were to maximize capability within the limit of device size, to be able to work in an IBM PC test station, and to be upwardly compatible with future products. Tradeoffs made for host synchronization, scan throughput, and more flexible commands reduce processor software overheard and improve scan and test rates. Evidence so far indicates that the SBM has met these goals. Prototype parts tested in a PC-based test system functioned as expected