Fast Simulation of SystemC Synthesizable Subset

Co-design and co-verification of complex SoC requires a virtual platform, which in an ideal case has the single source codes with hardware blocks included. An effective way to do that is using the SystemC language together with high level synthesis technology. Execution of the virtual platform requires simulation of SystemC parts, which is quite time-consuming. We present an approach to accelerate SystemC simulation that is based on reducing a number of SystemC process context switches. This approach is implemented in the FastSim component that contains a few SystemC-inherited classes. Use of Fast Sim requires small changes in the design, and no changes in the SystemC kernel. We have evaluated Fast Sim on an industrial SoC with a number of hardware accelerators and CPU cores. For this project, Fast Sim provides x450 simulation performance boost.