Systematic, non-defect, yield and performance optimization on 90, 65 & 45nm microprocessors

Author

Poindexter, Daniel ; Walsh, Brian ; Clougherty, Frances ; Tetzloff, Jon ; Thomas, David ; Rizzolo, Richard ; Salem, Gerard ; Crafts, James ; Nelson, Erik

Author_Institution

IBM Syst. & Technol. Group, Hopewell Junction, NY, USA

fYear

2010

Firstpage

92

Lastpage

98

Abstract

Key elements of systematic yield optimization used for SOI 90, 65 & 45nm microprocessors performing between 1.5 - 5 GHz (Table 1) will be reviewed. A method for isolating, measuring and acting upon systematic yield elements is shown. Models for optimizing performance limited yield and optimizing FET performance for maximum yield are reviewed. Finally, techniques for ship product quality level yield optimization are shown.

Keywords

circuit optimisation; field effect transistors; microprocessor chips; performance evaluation; FET performance; frequency 1.5 GHz to 5 GHz; microprocessor; performance optimization; ship product quality level yield optimization; size 45 nm; size 65 nm; size 90 nm; systematic yield element; systematic yield optimization; Delay; FETs; Logic gates; Microprocessors; Random access memory; Ring oscillators; Systematics;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI

Conference_Location

San Francisco, CA

ISSN

1078-8743

Print_ISBN

978-1-4244-6517-0

Type

conf

DOI

10.1109/ASMC.2010.5551429

Filename

5551429