A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS

A CDR circuit for serial link receivers usually requires a multi-phase generator and a number of phase rotators to produce data and edge clocks. The most commonly used architecture is a dual-loop CDR where a DLL (or PLL) generates k equidistantly spaced clock phases that are fed into n/2 phase rotators, where n is the number of sampling latches in the CDR. Another method was proposed, where the multi-phase generation and phase shifting is achieved at the same time in a single PLL, in this case achieving phase-adjustment capability through the weighted summing of charge-pump outputs for several phases. This approach eliminates the additional delay associated with using phase rotators and simplifies the overall design. However, all these conventional methods require either a PLL or a DLL, blocks that demand the largest share of power consumption and of silicon area in the CDR circuit. An alternate approach to implementing a phase generator and rotator is described in this paper, with the basic design concept of this approach is also illustrated.