A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects

Short-distance parallel optical links are poised to replace copper interconnects in high throughput links between computing nodes. In the receiver front-end of such systems, one- and two-dimensional monolithically integrated arrays of power- and area-efficient TIAs are required. Differential signaling is preferred for superior supply rejection while power consumption per amplifier unit should be minimized to avoid heat dissipation issues and to maintain the energy efficiency (J/bit) advantage over copper interconnect. On the other hand, lower gain is acceptable due to the intended short-haul application. Multi-Gb/s CMOS TIAs suffer from a fundamental BW limit at the input. The TIA input sees significant extrinsic capacitive loading (C_IN), not only from the photodiode (C_PD) which is dominant, but also from the ESD structures (C_ESD) and the offset-cancellation circuit (C_OC), which is needed due to finite extinction ratio of the transmitter laser diodes. The impact is more severe in CMOS as the input impedance of the circuit (1/g_m) is relatively high due to the low g_m/l_D of CMOS technology. The regulated cascode approach is an effective BW-extension technique that desensitizes the circuit to input capacitance by reducing the TIA input impedance through negative feedback. However, in its conventional implementation, power dissipation is increased due to the additional broadband feedback amplifier while stability can be compromised by phase shifts. In this work, the voltage gain available from the common-gate TIA front-end is reused for the compensation rather than employing a dedicated amplifier; with the aim of demonstrating a more power- and area-efficient approach to CMOS BW extension.