Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques

Serial based FPGA fault emulation schemes for probabilistic errors rely on a random number generator -- which is used for generation of fault bits - and a shift register - used for placing the fault bits to their corresponding fault location. It has two advantages with respect to parallel solutions: lower cost and better accuracy. The main disadvantage is represented by the high emulation overhead: for each emulation clock cycle, a number of clock cycles equal to the number of fault locations is required to load the shift register. This paper presents a technique for FPGA probabilistic fault emulation which reduces the emulation overhead, at the expense of accuracy. It is based on pseudo-random permutations within the shift register, while maintaining the number of active fault bits. We obtain a performance improve of one order of magnitude, while we have a cost increase of 27% and lower fault modeling accuracy.