Parameterized Critical Path Selection for Delay Fault Testing

Delay faults testing is more and more important due to huge number of gates and lines integrated on a chip. Path delay faults are tested via selected critical paths in a tested digital circuit. The critical paths can be specified e.g. By static timing analysis (STA), statistical static timing analysis (SSTA) and others. Signal delay propagation is also affected by many factors such as power supply noise, multiple input switching, temperature and others during test. The impact of each factor to the path delay faults has been individually solved and published in some papers but their joint effects should be also investigated. A new technique for evaluation of critical paths and a general system for critical paths selection PaCGen have been developed and they are presented in the paper. It is based on STA and influences of multiple factors defined by the new technique for path criticality calculation. Some critical paths can be found as untestable based on structure of the circuit. The proposed system includes more effective DFT technique to change untestable critical paths to testable. Evaluation of the proposed technique has been done over ISCAS-89 benchmark circuits and compared with published results.